LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

ENTITY FDivider IS
  PORT (
    -- CLOCK signal
    CLK : IN STD_LOGIC;
    -- Divided CLOCK signal
    DCLK : OUT STD_LOGIC;
    -- RESET signal
    RST : IN STD_LOGIC
  );
END FDivider;

ARCHITECTURE FDivider OF FDivider IS

  SIGNAL count : STD_LOGIC_VECTOR(27 DOWNTO 0);
  SIGNAL clk_out : STD_LOGIC := '1';

BEGIN
  DCLK <= clk_out;

  divide_pro : PROCESS (CLK, RST)
  BEGIN
    IF (RST = '0') THEN
      -- asynchronous reset signal count, as soon as RST comes
      count <= "0000000000000000000000000000";
    ELSIF (CLK'event AND CLK = '1') THEN
      IF (count < "0001011111010111100001000000") THEN
        count <= count + 1;
      ELSE
        clk_out <= NOT clk_out;
        count <= "0000000000000000000000000000";
      END IF;
    END IF;
  END PROCESS; -- divide_pro

END FDivider; -- FDivider